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Google patents dynamic cache mode switching for system performance

Google describes a method for a system-level cache to dynamically switch between a normal mode and a victim cache mode. The system monitors performance metrics and switches modes when specific criteria are met to optimize how memory requests are handled.

Why it mattersThis improves how computer systems manage memory efficiency, which is a routine but important part of chip design.

In the filing’s own words

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for dynamically selecting a cache mode. One of the methods includes operating a system-level cache (SLC) in a victim cache mode by implementing a portion of the SLC as a victim cache partition for a first cache. The method further includes monitoring a performance metric for the victim cache partition. When the performance metric meets one or more switching criteria, the first cache and the SLC are operated in a normal cache mode.

What exactly they claim (claim 1)

1. A system comprising: a memory device; a system-level cache (SLC) configured to cache memory requests to the memory device; a plurality of client devices configured to provide memory requests through the SLC to the memory device, wherein a first client device has a first cache that is higher in a cache hierarchy than the SLC, wherein the system is configured to operate the first cache in a victim cache mode, wherein the system is configured to operate the SLC in a victim cache mode by implementing a portion of the SLC as a victim cache partition for the first cache while also serving memory requests for other client devices of the plurality of other client devices, and wherein the system is configured to monitor a performance metric for the victim cache partition and, upon determining that the performance metric meets one or more switching criteria, to operate the first cache and the SLC in a normal cache mode instead of the victim cache mode.

Facts

Company
Google (Google LLC)
Official title
DYNAMIC CONTROL OF CACHE MODE
Publication number
US20260277806A1
Application number
19166689
Filed
Mar 22, 2023
Published
Sep 17, 2026
Inventors
5
Claims
21

Classified under

G06F 12/0802 Physics & computingG06F 2212/60 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.