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Google patents memory scheduling for AI workloads

Google has filed a patent for a method to manage how data is accessed in memory while running machine learning tasks. The system adjusts the priority of AI calculations and the speed of the memory chip to ensure both the AI workload and standard data requests finish on time.

Why it mattersThis is interesting for tech enthusiasts because it shows how hardware engineers are optimizing memory chips to handle the heavy data demands of AI without slowing down other computer tasks.

In the filing’s own words

Methods, systems, and apparatus, including computational instructions/programs encoded on non-transitory computer-readable media, are disclosed for command and memory access scheduling at an integrated circuit. A system determines a performance target for executing an ML workload and based on a first priority, schedules commands for compute operations for executing the workload at a processor-in-memory (“PiM”) block of a memory device. For concurrent memory transactions of both PiM commands for the compute and memory access requests, the system determines a prospective violation of the performance target for the workload and addresses the prospective violation by adjusting the first priority to exceed a second priority assigned to the memory requests. The system satisfies both the performance targets for executing the ML workload at the PiM block and processing memory requests by adjusting the first priority to exceed the second priority and adjusting an operating frequency of the memory device and PiM block.

What exactly they claim (claim 1)

1. A method implemented using an integrated circuit comprising a System-on-Chip (“SoC”) and a memory device coupled to the SoC, the method comprising: determining a performance target for executing a machine-learning (ML) workload; scheduling, based on a first priority, commands for compute operations at a processor-in-memory (“PiM”) block of the memory device to execute the ML workload at the integrated circuit; determining a prospective violation of the performance target; addressing the prospective violation by adjusting the first priority to exceed a second priority assigned to memory read/write transactions provided to the memory device; and satisfying the performance targets of the ML workload at the PiM block and memory read/write transactions in response to adjusting the first priority to exceed the second priority and adjusting an operating frequency of the memory device and the PiM block.

Facts

Company
Google (Google LLC)
Official title
MEMORY ACCESS SCHEDULING FOR PARALLEL COMPUTATIONS USING A PROCESSING-IN-MEMORY ARCHITECTURE
Publication number
US20260277679A1
Application number
19167078
Filed
Feb 27, 2025
Published
Sep 17, 2026
Inventors
3
Claims
23

Classified under

G06F 9/5016 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.