Samsung patents storage method to time data from memory chips
Samsung has filed a patent for a storage device that manages how data leaves multiple memory chips. The system uses a controller to send specific timing signals that delay when the second chip starts sending data, preventing overlap on the shared data line.
In the filing’s own words
A storage device includes non-volatile memory dies, and a memory controller that outputs a first data output command address packet and receives first data. The memory controller receives the first data from a first non-volatile memory die through a data bus, and sequentially outputs a second data output command packet that instructs a second non-volatile memory die among the plurality of non-volatile memory dies to output second data, a second select chip enable packet that selects the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die. The second select chip enable packet includes a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first delay information for delaying an output point in time of the second data.
What exactly they claim (claim 1)
1. A storage device comprising: a non-volatile memory device including a plurality of non-volatile memory dies; and a memory controller configured to: transmit a first data output command address packet to a first non-volatile memory die among the plurality of non-volatile memory dies, through a command address bus, receive a first data from the first non-volatile memory die through a data bus, and sequentially transmit a second data output command packet to a second non-volatile memory die among the plurality of non-volatile memory dies, a second select chip enable packet that selects the second non-volatile memory die to the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die to the first non-volatile memory die, through the command address bus, and wherein the second select chip enable packet comprises a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first information related to a second data transferred through the data bus.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- STORAGE DEVICE, MEMORY CONTROLLER, NON-VOLATILE MEMORY DEVICE, AND METHOD OF OPERATING MEMORY CONTROLLER FOR CONTROLLING DATA OUTPUT TIMING
- Publication number
- US20260277490A1
- Application number
- 19680423
- Filed
- May 18, 2026
- Published
- Sep 17, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06F 3/0659 Physics & computingG06F 3/0604 Physics & computingG06F 3/0679 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.