/Patent Tracker
GooglePatent applicationChips & hardwareInterest 4/10

Google patents chip design that reads data in variable-sized chunks

This filing describes a method for a hardware chip to read data from its internal memory in specific, variable-length sequences rather than fixed blocks. It uses a specific instruction code to determine how many consecutive bytes to pull from the memory banks to create input vectors for processing.

Why it mattersThis is a low-level engineering detail that could help hardware designers build more efficient data pipelines for specialized processors, though it does not describe a consumer-facing feature.

In the filing’s own words

Methods and systems, including computer-readable media, are described for a byte stream processing pipeline using an instruction set architecture for a hardware integrated circuit. The byte stream pipeline is used to access memory banks of a compute tile of the circuit based on an instruction executed at the tile. An opcode is identified in the instruction. The opcode indicates an operation to access memory banks of a memory at the tile. From the opcode, a byte addressing sequence is generated to access different lengths of contiguous bytes that are stored at the banks. Based on the byte addressing sequence, multiple byte-addressable memory accesses are performed at the memory to obtain a plurality of input vectors from the memory banks.

What exactly they claim (claim 1)

1. A computer-implemented method for accessing memory banks of a hardware accelerator, the method comprising: receiving an instruction for a compute tile of the hardware accelerator, the instruction being executable at the compute tile to cause performance of operations comprising: identifying, in the instruction, an opcode for an operation that involves accessing one or more banks of a first memory of the compute tile; generating, based on the opcode, a byte addressing sequence used to access different lengths of contiguous bytes stored at the one or more banks; based on the byte addressing sequence, performing, at the first memory, a plurality of byte-addressable memory accesses to obtain a plurality of input vectors from the one or more banks of the first memory; and processing, based on the instruction, the plurality of input vectors at the hardware accelerator.

Facts

Company
Google (Google LLC)
Official title
BYTE STREAM PROCESSING PIPELINE FOR A HARDWARE INTEGRATED CIRCUIT
Publication number
US20260277465A1
Application number
19167983
Filed
Mar 25, 2024
Published
Sep 17, 2026
Inventors
3
Claims
20

Classified under

G06F 3/0655 Physics & computingG06F 3/0604 Physics & computingG06F 3/0679 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

More from Google in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.