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Samsung patents chip stacking method with uneven protective layers

Samsung describes a way to build semiconductor packages by stacking multiple chips on top of each other. The design uses small holes called through vias to connect electrical contacts on the front and back of each chip, allowing them to link vertically. A key feature is that the protective coating around the front contacts has a thickness that changes depending on its position.

Why it mattersThis filing focuses on the physical construction of computer chips, which is a routine but essential part of making processors smaller and more efficient.

In the filing’s own words

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.

What exactly they claim (claim 1)

1. A semiconductor package, comprising: a substrate extending in a first direction and a second direction perpendicular to the first direction; semiconductor chips stacked on the substrate; and a molding layer on the substrate, the molding layer surrounding the semiconductor chips, wherein each of the semiconductor chips includes: a semiconductor substrate having a first surface and a second surface that are opposite to each other; a semiconductor element on the first surface of the semiconductor substrate; first pads on the semiconductor element and a first passivation layer that surrounds the first pads and exposes one surface of each of the first pads; second pads on the second surface of the semiconductor substrate and a second passivation layer that surrounds the second pads and exposes one surface of each of the second pads; and through vias that penetrate, in a third direction perpendicular to the first direction and the second direction, the semiconductor substrate and connect the first pads to the second pads, wherein, for two adjacent ones of the stacked semiconductor chips, the first pads of a first one of the two adjacent semiconductor chips are respectively in contact with the second pads of a second one of the two adjacent semiconductor chips, and wherein a thickness, in the third direction, of the first passivation layer varies based on position along the first direction.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Publication number
US20260271795A1
Application number
19666446
Filed
May 4, 2026
Published
Sep 10, 2026
Inventors
6
Claims
20

Classified under

H10W 90/00 Electricity & electronicsH10W 20/023 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 72/019 Electricity & electronicsH10W 90/297 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.