Samsung patents chip layout with controller sandwiched between two processors
Samsung describes a semiconductor package where a controller is placed physically between two separate chip structures on a baseboard. The design uses specific wiring patterns to connect the controller's edges and center points to the baseboard, allowing the three components to work together in a compact arrangement.
In the filing’s own words
A semiconductor package includes a substrate, a first chip structure disposed on the substrate, a second chip structure disposed on the substrate, at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed on edges opposing each other in a first direction, and center pads disposed between the edge pads, and bonding wire structures. The substrate includes first bonding pads arranged in a second direction, perpendicular to the first direction, and second bonding pads arranged in the second direction in at least one of a space between the first bonding pads and the first chip structure and a space between the first bonding pads and the second chip structure. The bonding wire structures include a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure connecting the center pads to the second bonding pads.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate including a wiring circuit; a first chip structure and a second chip structure disposed on the substrate, and spaced apart from each other in a first direction; at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed at respective edges opposite each other in the first direction, and center pads disposed between the edge pads in the first direction; and bonding wire structures electrically connecting the first chip structure, the second chip structure, and the at least one controller to the wiring circuit of the substrate, wherein the substrate includes: first bonding pads disposed between the first chip structure and the at least one controller and between the second chip structure and the at least one controller, and second bonding pads disposed between the first bonding pads and at least one of the first chip structure and the second chip structure, wherein the bonding wire structures include: a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure directly connecting the center pads to the second bonding pads.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260271790A1
- Application number
- 19664322
- Filed
- Apr 30, 2026
- Published
- Sep 10, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 72/30 Electricity & electronicsH10W 72/50 Electricity & electronicsH10W 72/851 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.