Samsung patents chip package design with two-layer molding
Samsung describes a method for building a semiconductor package that holds two chips using two separate layers of protective plastic. The design places one chip next to another, connects them via a bridge called an interposer, and encases them in a specific order to secure the connections.
In the filing’s own words
A semiconductor package includes a package substrate, an interposer on the package substrate, a lower molding layer on the package substrate and surrounding the interposer, a first semiconductor chip on the lower molding layer, a chip connection terminal between the first semiconductor chip and the package substrate and surrounded by the lower molding layer, a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip, interposer connection terminals that connect the first and second semiconductor chips to the interposer, and an upper molding layer on the lower molding layer and surrounding the first and second semiconductor chips.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor package, the method comprising: mounting a first semiconductor chip and a second semiconductor chip on a mold frame, the second semiconductor chip being at an outer side of the first semiconductor chip; forming an upper molding layer on the mold frame, the upper molding layer surrounding the first semiconductor chip and the second semiconductor chip; removing the mold frame; forming a first conductive pillar on a bottom surface of the first semiconductor chip, forming a second conductive pillar at an outer side of the first conductive pillar, forming a third conductive pillar on a bottom surface of the second semiconductor chip, and mounting a chip connection terminal on the first conductive pillar; electrically connecting the first semiconductor chip and the second semiconductor chip through an interposer; electrically connecting the first semiconductor chip to a package substrate by connecting the chip connection terminal to an upper package substrate pad of the package substrate; and forming a lower molding layer between the upper molding layer and the package substrate, the lower molding layer surrounding the interposer, the first conductive pillar, and the chip connection terminal.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260271749A1
- Application number
- 19661104
- Filed
- Apr 28, 2026
- Published
- Sep 10, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 70/611 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/401 Electricity & electronicsH10W 72/072 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.