Samsung patents chip wiring with uneven metal layers
This filing describes a method for building tiny electrical connections inside a computer chip. It uses different metal materials, specifically a ruthenium-cobalt mix and pure cobalt, in two separate layers to create a specific height difference between the wires.
In the filing’s own words
Provided is a semiconductor device including a substrate including an active region, transistors on the substrate, a first interlayer insulating layer and a second interlayer insulating layer on the transistors, a first interconnection line in an upper portion of the first interlayer insulating layer, and a second interconnection line in the second interlayer insulating layer, wherein the first interconnection line includes a first barrier pattern, a first liner, and a first conductive pattern, wherein the second interconnection line includes a second barrier pattern, a second liner, and a second conductive pattern, wherein first height between an uppermost portion of a top surface of the first conductive pattern and a lowermost portion of a top surface of the first liner is greater than a second height between an uppermost portion of a top surface of the second conductive pattern and a lowermost portion of a top surface of the second liner.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming transistors on an active region of a substrate; forming a first interlayer insulating layer on the transistors; forming a first interconnection line in an upper portion of the first interlayer insulating layer; forming a second interlayer insulating layer on the first interlayer insulating layer; and forming a second interconnection line in the second interlayer insulating layer and electrically connected to the first interconnection line, wherein forming the first interconnection line comprises: forming a first barrier pattern; forming a first liner including a ruthenium cobalt (RuCo) compound on the first barrier pattern; forming a first conductive pattern on the first liner; and performing a first planarization process, wherein forming the second interconnection line comprises: forming a second barrier pattern; forming a second liner including cobalt (Co) on the second barrier pattern; forming a second conductive pattern on the second liner, and performing a second planarization process, wherein the first planarization process forms a first recess on top surface of the first liner, wherein the second planarization process forms a second recess on top surface of the second liner, wherein a first height between an uppermost point of a top surface of the first conductive pattern and a lowermost point of a portion of a top surface of the first liner, that is continuous with the top surface of the first conductive pattern, is less than a second height between an uppermost point of a top surface of the second conductive pattern and a lowermost point of a portion of a top surface of the second liner that is continuous with the top surface of the second conductive pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260271699A1
- Application number
- 19662659
- Filed
- Apr 29, 2026
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 20/42 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/0167 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.