Samsung patents chip design using air gaps to connect wiring layers
Samsung has filed a patent for a semiconductor device that places a small pocket of air between two vertical connections in a chip. This design helps link the main processing parts on one side of the chip to wiring lines on the back side.
In the filing’s own words
A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device comprising: forming a first source/drain pattern and a second source/drain pattern on a first surface of a substrate, wherein the substrate includes the first surface and a second surface opposite to the first surface in a first direction, and the first source/drain pattern and the second source/drain pattern are spaced apart from each other in a second direction; forming a first upper interlayer insulating layer covering the first source/drain pattern and the second source/drain pattern on the first surface of the substrate; forming a first contact connection via penetrating the first upper interlayer insulating layer, laterally adjacent to the first source/drain pattern; forming a second contact connection via penetrating the first upper interlayer insulating layer, laterally adjacent to the second source/drain pattern; forming an air gap structure between the first contact connection via and the second contact connection via; forming a first source/drain contact on the first source/drain pattern, wherein the first source/drain contact electrically connects the first source/drain pattern with the first contact connection via; forming a second source/drain contact on the second source/drain pattern, wherein the second source/drain contact electrically connects the second source/drain pattern with the second contact connection via; and forming a rear wiring line on the second surface of the substrate, wherein the rear wiring line is electrically connected to the first contact connection via and the second contact connection via.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260271694A1
- Application number
- 19536762
- Filed
- Feb 11, 2026
- Published
- Sep 10, 2026
- Inventors
- 8
- Claims
- 20
Classified under
H10W 20/20 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/024 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6211 Electricity & electronicsH10D 30/6219 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.