Samsung patents chip design with stacked insulation to separate transistors
This filing describes a semiconductor structure where two transistor channels are separated by a specific insulating barrier. The barrier is made of two stacked layers, with the joint between them positioned lower than the top of the transistor channels.
In the filing’s own words
A semiconductor device includes a first channel pattern and a second channel pattern spaced apart from each other in a first direction on a substrate, a first gate electrode on the first channel pattern and extending in the first direction, a second gate electrode on the second channel pattern and extending the first direction, and a separation insulating pattern between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode are aligned with each other in the first direction. The separation insulating pattern includes a lower pattern and an upper pattern stacked in a vertical direction perpendicular to a top surface of the substrate. An interface between the lower pattern and the upper pattern is located at a lower height than an uppermost surface of the first channel pattern and an uppermost surface of the second channel pattern.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first channel pattern and a second channel pattern spaced apart from each other in a first direction on a substrate having a top surface and a bottom surface opposite the top surface; a first gate electrode on the first channel pattern and extending in the first direction; a second gate electrode on the second channel pattern and extending in the first direction; and a separation insulating pattern between the first gate electrode and the second gate electrode, wherein the first gate electrode and the second gate electrode are aligned with each other in the first direction, wherein the separation insulating pattern includes a lower pattern and an upper pattern stacked in a vertical direction perpendicular to the top surface of the substrate, and wherein an interface between the lower pattern and the upper pattern is positioned at a lower height than an uppermost surface of the first channel pattern and an uppermost surface of the second channel pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260271689A1
- Application number
- 19455390
- Filed
- Jan 21, 2026
- Published
- Sep 10, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 10/20 Electricity & electronicsH10D 84/832 Electricity & electronicsH10W 10/17 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/0153 Electricity & electronicsH10W 10/014 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.