Samsung patents chip design with smooth gate structures
Samsung has filed a patent for a semiconductor device that uses a specific shape for the gate structures on a chip. The design features a gate that slopes downward near a trench, ensuring the surface height changes gradually rather than abruptly.
In the filing’s own words
A semiconductor device including a substrate including a trench, an isolation structure including an inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern on a surface of the trench, and a gate structure on a top surface of the substrate and a portion of a top surface of the isolation structure. The upper surface of the gate structure disposed on the top surface of the substrate is higher than an upper surface of the gate structure disposed on the portion of the top surface of the isolation structure. The upper surface of the gate structure has a downward slope from a boundary between an uppermost surface of the inner wall oxide layer pattern and an upper surface of the substrate toward the inner wall oxide layer, and a portion of an upper surface of the isolation structure adjacent to the trench has no discontinuous change in height.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including a trench having a first inner side, a bottom and a second inner side facing the first inner side; an isolation structure filling the trench, the isolation structure including an inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern sequentially stacked on a surface of the trench; and a gate structure on a top surface of the substrate and a portion of a top surface of the isolation structure, and an edge portion of the gate structure covering upper portions of the inner wall oxide layer pattern, the liner pattern and the filling insulation pattern adjacent to the first inner side of the trench, wherein an upper surface of the gate structure disposed on the top surface of the substrate is higher than an upper surface of the gate structure disposed on the portion of the top surface of the isolation structure, wherein the upper surface of the gate structure on the isolation structure has a downward slope from a boundary between an uppermost surface of the inner wall oxide layer pattern and an upper surface of the substrate toward the inner wall oxide layer, wherein at least a portion of an upper surface of the isolation structure adjacent to the trench has no discontinuous change in height.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260271684A1
- Application number
- 19468389
- Filed
- Feb 3, 2026
- Published
- Sep 10, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 10/014 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/50 Electricity & electronicsH10D 64/512 Electricity & electronicsH10D 64/516 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.