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Samsung patents method to check chip layer alignment using electron beam images

This filing describes a way to measure how well different layers of a computer chip line up during manufacturing. It uses a special marker and an electron beam scan to create an image that helps engineers calculate any misalignment between the layers.

Why it mattersThis is a routine improvement in chip manufacturing quality control that helps ensure tiny electronic components are built correctly.

In the filing’s own words

An overlay measuring method includes placing a lower pattern and an upper pattern in a layout, shifting at least one of the lower pattern and the upper pattern by a programmed misalignment, adding a programmed mark in the layout, forming a lower conductive pattern, an upper conductive pattern, and a mark structure on a key region of a substrate, based on the layout, the mark structure being formed by the programmed mark, performing an e-beam inspection on the key region to obtain a voltage contrast (VC) image, the VC image including a reference mark that is a signal of the mark structure, matching an actual measuring region of the VC image to the layout using the reference mark, and obtaining an overlay value in the key region.

What exactly they claim (claim 1)

1. An overlay measuring method comprising: placing a lower pattern and an upper pattern in a layout; shifting at least one of the lower pattern and the upper pattern by a programmed misalignment; adding a programmed mark in the layout; forming a lower conductive pattern, an upper conductive pattern, and a mark structure on a key region of a substrate, based on the layout, the mark structure being formed by the programmed mark; performing an e-beam inspection on the key region to obtain a voltage contrast (VC) image, the VC image including a reference mark that is a signal of the mark structure; matching an actual measuring region of the VC image to the layout using the reference mark; and obtaining an overlay value in the key region.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
OVERLAY MEASURING METHOD USING A VOLTAGE CONTRAST IMAGE
Publication number
US20260271395A1
Application number
19660887
Filed
Apr 28, 2026
Published
Sep 10, 2026
Inventors
8
Claims
20

Classified under

H10D 84/853 Electricity & electronicsG03F 7/70633 Physics & computingG03F 7/70683 Physics & computingH10B 12/01 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/482 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.