Samsung patents nanosheet chip design with new insulating spacers
Samsung describes a transistor structure using a thin sheet of silicon, called a nanosheet, wrapped by a gate line to control electricity flow. The design adds specific insulating walls and spacers to isolate the components and prevent electrical leakage between the source and drain regions.
In the filing’s own words
An integrated circuit device includes at least one nanosheet, a pair of source/drain regions contacting the at least one nanosheet, a gate line between the pair of source/drain regions in a first horizontal direction and surrounding the at least one nanosheet, an insulating wall structure having a first sidewall contacting the pair of source/drain regions and facing the gate line, a gate dielectric film surrounding the gate line, and a pair of blocking insulating spacers arranged, in a plan view, in a gap area between the first sidewall and the gate line, in a second horizontal direction, and respectively contacting the pair of source/drain regions, wherein the pair of blocking insulating spacers are spaced apart from one another in the first horizontal direction in the gap area and each include a portion contacting the gate dielectric film and a portion contacting the first sidewall of the insulating wall structure.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a nanosheet stack comprising at least one nanosheet; a pair of source/drain regions spaced apart from one another in a first horizontal direction with the nanosheet stack therebetween, each of the pair of source/drain regions being in contact with the at least one nanosheet; a gate line arranged between the pair of source/drain regions in the first horizontal direction and surrounding the at least one nanosheet; an insulating wall structure arranged adjacent to the nanosheet stack, the gate line, and the pair of source/drain regions in a second horizontal direction intersecting the first horizontal direction, the insulating wall structure having a first sidewall that includes portions contacting the pair of source/drain regions and a portion facing the gate line; a gate dielectric film surrounding the gate line; and a pair of blocking insulating spacers each arranged, in a plan view, in a gap area between the first sidewall of the insulating wall structure and the gate line, in the second horizontal direction, and contacting the pair of source/drain regions, wherein the pair of blocking insulating spacers are spaced apart from one another in the first horizontal direction in the gap area and each comprise a portion contacting the gate dielectric film and a portion contacting the first sidewall of the insulating wall structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260271393A1
- Application number
- 19332522
- Filed
- Sep 18, 2025
- Published
- Sep 10, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 84/852 Electricity & electronicsH10D 84/0167 Electricity & electronicsH10D 84/017 Electricity & electronicsH10D 84/0186 Electricity & electronicsH10D 84/0188 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.