Samsung patents chip design with stacked contacts for better wiring
Samsung describes a semiconductor device layout where the electrical connections to the chip's control gate and data channels are arranged in a specific stacked configuration. The design uses a lower contact and an upper contact for the data channels, allowing wiring to connect to different levels within the chip structure.
In the filing’s own words
A semiconductor device includes an active pattern extending on a substrate in a first direction; a gate structure extending on the active pattern in a second direction, the gate structure intersecting the first direction, the gate structure including a gate electrode; a source/drain pattern on at least one side of the gate structure; a source/drain contact including a lower contact and an upper contact protruding from a region of the lower contact on the source/drain pattern; a gate contact on a region of the gate electrode; an insulating molding layer covering the source/drain contact, the gate structure, and the gate contact; and an interconnection line on the insulating molding layer, the interconnection line having a first via connected to the upper contact of the source/drain contact and a second via connected to the gate contact.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: an active pattern extending on a substrate in a first direction; a gate structure extending on the active pattern in a second direction, the gate structure intersecting the first direction, the gate structure including a gate electrode; a source/drain pattern on at least one side of the gate structure; a source/drain contact including a lower contact on the source/drain pattern and an upper contact protruding from a region of the lower contact; a gate contact on a first region of the gate electrode; an insulating molding layer covering the source/drain contact, the gate structure, and the gate contact; and an interconnection line on the insulating molding layer, the interconnection line having a first via connected to the upper contact of the source/drain contact and a second via connected to the gate contact.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260271382A1
- Application number
- 19531204
- Filed
- Feb 5, 2026
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/832 Electricity & electronicsH10D 30/503 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 64/256 Electricity & electronicsH10D 64/518 Electricity & electronicsH10D 64/62 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.