Samsung patents memory chip design with stepped wiring layers
Samsung has filed a patent for a semiconductor memory device that uses a specific layout to connect its storage cells to control circuits. The design features word lines with a stepwise shape and groups of four vertical connections that pass through insulating patterns to link the two main parts of the chip.
In the filing’s own words
A semiconductor memory device includes a cell structure; and a peripheral circuit structure on the cell structure, wherein the cell structure includes a first substrate, stack structures spaced apart from one another in a first horizontal direction on the substrate, including word lines spaced apart from one another in a vertical direction, each word line having a stepwise shape, word line contacts electrically connected to the word lines, and landing pads electrically connected to the word line contacts, the peripheral circuit structure includes a second substrate, insulating patterns passing through the second substrate, and through vias electrically connected to the landing pads, each of the through vias constitutes via groups including first to fourth through vias adjacent to one another, and the first to fourth through vias of the via groups pass through the insulating patterns, respectively.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a cell structure; and a peripheral circuit structure on the cell structure, wherein: the cell structure includes a first substrate, stack structures spaced apart from one another in a first horizontal direction on the substrate, including word lines spaced apart from one another in a vertical direction, each word line having a stepwise shape, word line contacts electrically connected to the word lines, and landing pads electrically connected to the word line contacts, the peripheral circuit structure includes a second substrate, insulating patterns passing through the second substrate, and through vias electrically connected to the landing pads, each of the through vias constitutes via groups including first to fourth through vias adjacent to one another, and the first to fourth through vias of the via groups pass through the insulating patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260271309A1
- Application number
- 19327997
- Filed
- Sep 12, 2025
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsH10B 12/30 Electricity & electronicsH10B 12/50 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.