Samsung patents stacked memory chip design with vertical connections
Samsung describes a semiconductor device where a memory section is stacked directly on top of a processing section. The design uses vertical plugs to connect the memory cells to the underlying circuitry, allowing the two parts to share space more efficiently.
In the filing’s own words
A semiconductor device includes a first structure including a memory cell region, and a second structure that overlaps the first structure in a vertical direction and includes a peripheral circuit region. The first structure includes memory cells disposed on the memory cell region, and a cell routing interconnection structure. The second structure includes a semiconductor body, a rear insulating layer, element isolation patterns that define respective peripheral active regions of the semiconductor body, peripheral transistors, each including a first peripheral source/drain and a second peripheral source/drain disposed within the peripheral active regions, a first through-insulating pattern that penetrates through the semiconductor body, and first through-plugs that penetrate through the first through-insulating pattern. The first through-plugs are spaced apart from each other in a horizontal direction and are electrically connected to the cell routing interconnection structure.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first structure including a memory cell region; and a second structure that overlaps the first structure in a vertical direction and includes a peripheral circuit region, wherein the first structure includes: memory cells disposed on the memory cell region, each memory cell including a memory cell transistor and an information storage structure connected to the memory cell transistor; and a cell routing interconnection structure that is electrically connected to the memory cells, wherein the second structure includes: a semiconductor body; a rear insulating layer below the semiconductor body; element isolation patterns that define respective peripheral active regions of the semiconductor body; peripheral transistors, each including a first peripheral source/drain, a second peripheral source/drain, a peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a peripheral gate disposed on the peripheral channel region, the first peripheral source/drain and the second peripheral source/drain being disposed within the peripheral active regions; a first through-insulating pattern that penetrates through the semiconductor body; and a plurality of first through-plugs that penetrate through the first through-insulating pattern, and wherein the plurality of first through-plugs are spaced apart from each other in a horizontal direction and are electrically connected to the cell routing interconnection structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260271287A1
- Application number
- 19535648
- Filed
- Feb 10, 2026
- Published
- Sep 10, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 43/10 Electricity & electronicsH10B 43/35 Electricity & electronicsH10W 20/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.