Samsung patents stacked chip design with vertical connections for memory
Samsung describes a semiconductor device where two chip layers are stacked vertically to save space. The design uses specific vertical wires, called through-vias, to connect the control circuits on the top layer to the memory storage area on the bottom layer.
In the filing’s own words
A semiconductor device according to an embodiment includes a first structure including a first substrate, wherein the first substrate includes a memory cell region and a first peripheral circuit region; a second structure overlapping the first structure in a vertical direction and including a second substrate, wherein the second substrate includes a core circuit region and a second peripheral circuit region; and peripheral through-vias penetrating the second substrate in the vertical direction and electrically connected to the first structure. The first peripheral circuit region includes peripheral active patterns, a peripheral bit line extending in the vertical direction and contacting the peripheral active patterns; peripheral gate electrodes overlapping the peripheral active patterns in the vertical direction; and a peripheral interconnection structure electrically connected to at least one of the peripheral bit line or the peripheral gate electrodes. The peripheral through-vias are electrically connected to the peripheral interconnection structure.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first structure including a first substrate, wherein the first substrate includes a memory cell region and a first peripheral circuit region; a second structure overlapping the first structure in a vertical direction and including a second substrate, wherein the second substrate includes a core circuit region and a second peripheral circuit region; and peripheral through-vias penetrating the second substrate in the vertical direction and electrically connected to the first structure, wherein the memory cell region includes: cell active patterns extending in a first horizontal direction and disposed to be spaced apart from each other in the vertical direction; a cell bit line extending in the vertical direction and contacting the cell active patterns; cell gate electrodes overlapping the cell active patterns in the vertical direction and extending in a second horizontal direction, intersecting the first horizontal direction; and a cell interconnection structure disposed on the cell active patterns, the cell bit line, and the cell gate electrodes, and electrically connected to at least one of the cell bit line or the cell gate electrodes, wherein the first peripheral circuit region includes: peripheral active patterns extending in the first horizontal direction; a peripheral bit line extending in the vertical direction and contacting the peripheral active patterns; peripheral gate electrodes overlapping the peripheral active patterns in the vertical direction and extending in the second horizontal direction; and a peripheral interconnection structure disposed on the peripheral active patterns, the peripheral bit line and the peripheral gate electrodes, and electrically connected to at least one of the peripheral bit line or the peripheral gate electrodes, wherein the peripheral through-vias are electrically connected to the peripheral interconnection structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES HAVING PERIPHERAL CIRCUIT REGIONS
- Publication number
- US20260271279A1
- Application number
- 19555298
- Filed
- Mar 3, 2026
- Published
- Sep 10, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 12/50 Electricity & electronicsH10B 12/09 Electricity & electronicsH10B 12/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.