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Samsung patents memory chip design with uneven word line thickness

Samsung describes a 3D memory structure where the control wires, or word lines, have two different thicknesses. One part of the wire is thinner to sit over the data storage area, while the other part is thicker to act as a pad in a separate region of the chip.

Why it mattersThis design tweak aims to improve how the memory cells are controlled and connected, which is a standard engineering step in making chips more efficient.

In the filing’s own words

A semiconductor memory device comprising a lower layer including first and second regions; a plurality of stacks on the lower layer, each of the stacks including interlayer insulating and channel patterns; bottom patterns disposed in the lower layer between the stacks; word lines provided between the interlayer insulating layers vertically adjacent to each other, the word lines crossing the channel patterns; bit lines extending along the first direction to cross the word lines in the first region and connect to first end portions of the channel patterns; and data storage elements connected to second end portions of the channel patterns in the first region. Each of the word lines includes a gate portion on the first region and a pad portion on the second region, and the gate portion has a first thickness and the pad portion has a second thickness different from the first thickness in the first direction.

What exactly they claim (claim 1)

1. A semiconductor memory device, comprising: a lower layer including a first region and a second region; a plurality of stacks spaced apart from each other on the lower layer, each of the plurality of stacks including interlayer insulating patterns and channel patterns, which are alternatingly stacked in a first direction perpendicular to a top surface of the lower layer; bottom patterns disposed in the lower layer between the stacks; word lines provided between the interlayer insulating layers vertically adjacent to each other, the word lines crossing the channel patterns and extending along a second direction that is parallel to the top surface of the lower layer; bit lines extending along the first direction to cross the word lines in the first region and connect to first end portions of the channel patterns; and data storage elements connected to second end portions of the channel patterns in the first region, wherein each of the word lines includes a gate portion on the first region and a pad portion on the second region, and wherein the gate portion has a first thickness and the pad portion has a second thickness different from the first thickness in the first direction.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE HAVING STACKED WORD LINES INCLUDING SUB-GATE ELECTRODES
Publication number
US20260271265A1
Application number
19662654
Filed
Apr 29, 2026
Published
Sep 10, 2026
Inventors
4
Claims
20

Classified under

H10B 12/30 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/05 Electricity & electronicsH10B 12/50 Electricity & electronicsH10B 80/00 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.