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Samsung patents memory chip with built-in self-checking computer

Samsung has filed a patent for a high-bandwidth memory (HBM) base die that includes a small, dedicated computer chip. This internal processor automatically records and timestamps data about how the memory is working, then sends these logs to the main computer system for review.

Why it mattersThis design allows memory chips to report their own health and performance issues directly, which could help engineers diagnose problems in high-speed computing systems more quickly.

In the filing’s own words

An HBM base die includes a plurality of HBM controller blocks each configured to manage command scheduling and data flow between a host interface and one or more memory devices of an HBM stack; a 3D DRAM PHY coupled to the one or more memory devices through a plurality of TSVs; a die-to-die interconnect configured to communicate with an adjacent die within a multi-die package; an NoC interconnect configured to couple internal subsystems of the HBM base die; and on-die debug logic comprising: a RISC microprocessor coupled to the NoC interconnect; an SRAM coupled to the RISC microprocessor and configured as a circular log buffer; and a DMA engine configured to transfer debug log data from the SRAM to a reserved memory region defined by a system bus mapping circuit; wherein the RISC microprocessor is configured to collect operational status information from one or more of the HBM controller blocks, the 3D DRAM PHY, and the die-to-die interconnect, timestamp the collected information, and store timestamped log entries in the SRAM.

What exactly they claim (claim 1)

1. A method of operating a high-bandwidth memory (HBM) base die including a near-memory computing subsystem, the method comprising: initializing, by a Reduced Instruction Set Computer (RISC) microprocessor on the HBM base die, a debug logging buffer in an on-die static random-access memory (SRAM); collecting, by the RISC microprocessor, operational status information from one or more subsystems of the HBM base die, the one or more subsystems including at least one HBM controller, a 3D DRAM physical interface (PHY), and a die-to-die interconnect; timestamping the collected operational status information and storing the timestamped information as log entries in the debug logging buffer; determining that a flush condition is satisfied based on the debug logging buffer; and initiating, responsive to the flush condition being satisfied, a direct-memory-access (DMA) transfer from the debug logging buffer to a reserved memory space accessible to a host device.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
HBM BASE DIE INCLUDING ON-DIE DEBUG LOGGING LOGIC
Publication number
US20260268997A1
Application number
19546277
Filed
Feb 20, 2026
Published
Sep 10, 2026
Inventors
3
Claims
20

Classified under

G11C 29/44 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.