Samsung patents 3D memory chip design with stacked layers and shared wiring
Samsung describes a memory device that stacks two semiconductor layers vertically to save space. The top layer holds the data storage cells, while the bottom layer contains the circuits that read and write that data, connected by vertical wires.
In the filing’s own words
A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.
What exactly they claim (claim 1)
1. A memory device, comprising: a first semiconductor layer comprising: a memory cell array; and a first bitline and a first complementary bitline extending in a first direction, disposed along a second direction crossing the first direction, and coupled with the memory cell array; a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, the second semiconductor layer comprising: a first bitline sense amplifier comprising a first pair of P-channel transistors and a first pair of N-channel transistors, and configured to control the first bitline and the first complementary bitline; and a first control line and a second control line coupled with the first bitline sense amplifier, wherein P-channel transistors of the first pair of P-channel transistors are disposed along the second direction, wherein N-channel transistors of the first pair of N-channel transistors are disposed along the second direction, wherein the first pair of P-channel transistors and the first pair of N-channel transistors are disposed along the first direction, and wherein the first control line is shared by the P-channel transistors of the first pair of P-channel transistors and the second control line is shared by the N-channel transistors of the first pair of N-channel transistors.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- MEMORY DEVICE WITH VERTICAL WIRING BETWEEN SEMICONDUCTOR LAYERS AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number
- US20260268966A1
- Application number
- 19658019
- Filed
- Apr 24, 2026
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 11/4097 Physics & computingG11C 5/063 Physics & computingG11C 11/4091 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.