Samsung patents 3D memory design with stacked data lines
Samsung describes a semiconductor chip where memory cells are stacked vertically in three dimensions. It uses two layers of wiring: lower 'local' lines connect directly to the cells, while higher 'global' lines group these local lines together to manage data flow.
In the filing’s own words
A semiconductor device may include: memory cells disposed three-dimensionally in a vertical direction, a first direction, and a second direction perpendicular to each other; local bit lines disposed at a same level in the vertical direction and connected to the memory cells; and global bit lines disposed at a higher level in the vertical direction than the local bit lines and connected to the local bit lines, wherein the global bit lines include: first global bit lines connected to N first local bit lines among the local bit lines, N may be a natural number equal to or greater than 2; and second global bit lines connected to N second local bit lines among the local bit lines. Each of the memory cells may include: a cell transistor including a cell gate electrode extending in the second direction; and a data storage structure.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: memory cells disposed three-dimensionally in a vertical direction, a first direction, and a second direction perpendicular to each other; local bit lines disposed at a same level in the vertical direction and connected to the memory cells; and global bit lines disposed at a higher level in the vertical direction than the local bit lines and connected to the local bit lines, wherein the global bit lines comprise: first global bit lines connected to N first local bit lines among the local bit lines, wherein N is a natural number equal to or greater than 2; and second global bit lines connected to N second local bit lines among the local bit lines, wherein each of the memory cells comprises: a cell transistor comprising a cell gate electrode extending in the second direction; and a data storage structure, wherein each of the first global bit lines comprises a first bit line portion, wherein each of the second global bit lines comprises a second bit line portion disposed at a higher level in the vertical direction than the first bit line portions of the first global bit lines, and wherein three local bit lines, sequentially disposed in the first direction among the local bit lines, are respectively connected to three global bit lines that are spaced apart among the global bit lines.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS AND GLOBAL BIT LINES
- Publication number
- US20260268946A1
- Application number
- 19553935
- Filed
- Mar 2, 2026
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 5/063 Physics & computingG11C 11/4091 Physics & computingG11C 11/4097 Physics & computingH10B 12/482 Electricity & electronicsH10B 12/485 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.