Samsung patents memory layout with split bit lines
Samsung describes a semiconductor memory design that separates vertical data lines into two distinct groups. It connects these groups to a control circuit using two transistors that switch on and off in opposite phases.
In the filing’s own words
A semiconductor memory device includes cell and peripheral structures. The cell structure includes first local bit lines extending in a vertical direction and spaced apart in a first horizontal direction, second local bit lines extending in the vertical direction and spaced apart from the first local bit lines in a second horizontal direction, a first global bit line extending in the first horizontal direction and electrically connected to the first local bit lines, and a second global bit line extending in the first horizontal direction and electrically connected to the second local bit lines. The peripheral circuit structure includes a peripheral circuit transistor, a first transistor electrically connected to the peripheral circuit transistor and the first global bit line, and a second transistor electrically connected to the peripheral circuit transistor and the second global bit line. The first and second transistors are selectively turned on in a complementary manner.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a cell structure; and a peripheral circuit structure on the cell structure, wherein the cell structure includes: first local bit lines which extend in a vertical direction on a first substrate, and are spaced apart in a first horizontal direction, second local bit lines which extend in the vertical direction on the first substrate, and are spaced apart from the first local bit lines in a second horizontal direction, a first global bit line which extends in the first horizontal direction, and is electrically connected to the first local bit lines, and a second global bit line which extends in the first horizontal direction, and is electrically connected to the second local bit lines, wherein the peripheral circuit structure includes: a peripheral circuit transistor on a second substrate, a first transistor which is electrically connected to the peripheral circuit transistor on the second substrate and the first global bit line, and a second transistor which is electrically connected to the peripheral circuit transistor on the second substrate and the second global bit line, wherein the first transistor and the second transistor are selectively turned on in a complementary manner.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260268945A1
- Application number
- 19370165
- Filed
- Oct 27, 2025
- Published
- Sep 10, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 5/063 Physics & computingG11C 11/4091 Physics & computingG11C 11/4097 Physics & computingH10B 12/482 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.