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Samsung patents chip layout tool that uses neural networks to find flaws

Samsung describes a method for improving the design of computer chips by using a neural network to spot weak spots in the layout. The system then fixes these issues and saves the improved design to a database for future use.

Why it mattersThis could help chip designers create more reliable processors by automatically identifying and fixing structural problems during the design phase.

In the filing’s own words

The layout optimization method may include defining information of a layout, deriving vulnerabilities of the layout by a vulnerability detector including a neural network model portion, performing optimization of the layout by an optimization module portion, and generating a new layout pattern by a layout database generator and updating the generated new layout pattern in a layout database.

What exactly they claim (claim 1)

1. A layout optimization method considering spatial and physical interactions between layers, the layout optimization method comprising: defining information of a layout; deriving vulnerabilities of the layout by a vulnerability detector including a neural network model portion; performing optimization of the layout by an optimization module portion; and generating a new layout pattern by a layout database generator and updating the generated new layout pattern in a layout database.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
METHOD AND SYSTEM FOR LAYOUT OPTIMIZATION
Publication number
US20260268060A1
Application number
19390950
Filed
Nov 17, 2025
Published
Sep 10, 2026
Inventors
5
Claims
20

Classified under

G06F 30/398 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.