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Microsoft patents faster data transfers by pre-loading address maps

Microsoft describes a method where a processor tells an input/output device where to send data before the transfer starts. It also sends a signal to a memory manager to pre-load the address translation needed for that data, saving time during the actual transfer.

Why it mattersThis is a low-level optimization that could make data transfers between hardware components slightly faster and more efficient.

In the filing’s own words

In one example of the present technology, a method includes sending, by a CPU core of a processor, a direct memory access (DMA) stream setup command to an input/output (I/O) device, the DMA stream setup command comprising a virtual address; and sending, from the CPU core of the processor, a prefetch message comprising the virtual address to an input/output memory management unit (IOMMU) to cause the IOMMU to: prefetch a translation of the virtual address into a corresponding physical address from a main memory; and store the translation of the virtual address into the corresponding physical address in a translation lookaside buffer (TLB) of the IOMMU.

What exactly they claim (claim 1)

1. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to prime a translation lookaside buffer (TLB) of an input/output memory management unit (IOMMU) by: sending, by a CPU core of the processor, a DMA stream setup command to an input/output (I/O) device, the DMA stream setup command comprising a virtual address; and sending, from the CPU core of the processor, a prefetch message comprising the virtual address to the IOMMU to cause the IOMMU to: prefetch a translation of the virtual address into a corresponding physical address from a main memory; and store the translation of the virtual address into the corresponding physical address in the TLB of the IOMMU.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
ADDRESS TRANSLATION PREFETCHING FOR INPUT/OUTPUT DEVICES
Publication number
US20260267807A1
Application number
19666726
Filed
May 4, 2026
Published
Sep 10, 2026
Inventors
2
Claims
20

Classified under

G06F 12/1063 Physics & computingG06F 12/0238 Physics & computingG06F 12/063 Physics & computingG06F 12/0862 Physics & computingG06F 12/1054 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.