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Google patents chip design that moves data between power zones

This filing describes a method for moving data between different parts of a computer chip that run at different speeds or voltage levels. It uses a series of switches and storage slots to shuffle data in a specific pattern, allowing the receiving side to reassemble the information correctly without needing a shared clock signal.

Why it mattersThis is a low-level engineering improvement that helps chips manage power and speed efficiently, which is a standard part of designing modern processors.

In the filing’s own words

An asynchronous FIFO system ( 300) for transferring data from a sending power domain ( 302) to a receiving power domain ( 304) on a chip includes a plurality of storage elements ( 308) and a plurality of cycling multiplexors ( 310, 312) in the sending power domain, a data toggling multiplexor ( 318) and a plurality of pointer generators ( 314, 316) in the receiving power domain, and a plurality of level shifters ( 322 a - d) arranged between the cycling multiplexors in the sending power domain ( 302) and other elements in the receiving power domain, wherein each pointer generator is configured to feed a respective pointer value to a respective cycling multiplexor to cause each cycling multiplexor to forward nonconsecutive data ( 1, 3, 5, 7 or 0, 2, 4, 6) from the plurality of storage elements ( 308), and wherein the data toggling multiplexor ( 318) is configured to read from the plurality of cycling multiplexors ( 310, 312) in a cycle to reconstruct data ( 0, 1, 2, 3, 4, 5, 6, 7, 8) in the plurality of storage elements in the receiving power domain.

What exactly they claim (claim 1)

1. An asynchronous FIFO system for transferring data from a sending power domain to a receiving power domain on a chip, the asynchronous FIFO system comprising: a plurality of storage elements and a plurality of cycling multiplexors in the sending power domain; a data toggling multiplexor and a plurality of pointer generators in the receiving power domain; and a plurality of level shifters arranged between the cycling multiplexors in the sending power domain and other elements in the receiving power domain, wherein each pointer generator is configured to feed a respective pointer value to a respective cycling multiplexor to cause each cycling multiplexor to forward nonconsecutive data from the plurality of storage elements, and wherein the data toggling multiplexor is configured to read from the plurality of cycling multiplexors in a cycle to reconstruct data in the plurality of storage elements in the receiving power domain.

Facts

Company
Google (Google LLC)
Official title
CROSSING FREQUENCY AND POWER DOMAINS
Publication number
US20260267604A1
Application number
19164960
Filed
Mar 20, 2023
Published
Sep 10, 2026
Inventors
2
Claims
12

Classified under

G06F 5/065 Physics & computingH03K 19/017509 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.