Samsung patents chip design with stacked nanosheets and selective gate contacts
Samsung describes a semiconductor structure where thin sheets of silicon, called nanosheets, are stacked in two groups separated by an insulating layer. A gate electrode wraps around the entire stack, but a conductive layer only touches the top and bottom surfaces of the upper sheets, leaving the sides uncovered.
In the filing’s own words
A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nanosheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a pattern extending in a first direction; a first lower nanosheet on the pattern; a second lower nanosheet on the first lower nanosheet; a separation layer on the second lower nanosheet; a first upper nanosheet on the separation layer; a second upper nanosheet on the first upper nanosheet; a gate electrode on the pattern and extending in a second direction, which crosses the first direction, the gate electrode surrounding each of the first lower nanosheet, the second lower nanosheet, the separation layer, the first upper nanosheet, and the second upper nanosheet; and a first layer between the gate electrode and a top surface of each of the first upper nanosheet and the second upper nanosheet, and between the gate electrode and a bottom surface of each of the first upper nanosheet and the second upper nanosheet, wherein a width of the first upper nanosheet in the second direction is greater than a width of the first layer in the second direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260262282A1
- Application number
- 19661245
- Filed
- Apr 28, 2026
- Published
- Sep 3, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/83 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6739 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.