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Samsung patents chip design that keeps different parts of a processor at the same height

Samsung describes a method for making semiconductor chips where the control gates in the main processing area and the surrounding support area are etched to be nearly the same height. The filing specifies that the difference in height between these two types of gates is kept under 10 nanometers to ensure a consistent surface profile.

Why it mattersThis is a routine manufacturing improvement that helps ensure chips are built with precise, uniform structures, which is standard practice for maintaining quality in advanced chip fabrication.

In the filing’s own words

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a first region and a second region; an active region on the first region and a peripheral active region on the second region; a channel pattern on the active region; a peripheral channel pattern on the peripheral active region; a first gate electrode on the channel pattern; and a second gate electrode on the peripheral channel pattern. A linewidth of the second gate electrode is larger than a linewidth of the first gate electrode, and a difference in height between the first and second gate electrodes is smaller than about 10 nm, and a top surface of the second gate electrode has a doubly-concave shape.

What exactly they claim (claim 1)

1. A method of manufacturing a semiconductor device, the method comprising: forming an active region on a first region of a substrate; forming a peripheral active region on a second region of the substrate; forming a channel pattern on the active region; forming a peripheral channel pattern on the peripheral active region; forming a gate electrode on the channel pattern; forming a peripheral gate electrode on the peripheral channel pattern; simultaneously performing a metal etching process on the first region and the second region to form a first recessed top surface in the gate electrode and a second recessed top surface in the peripheral gate electrode; and forming gate capping patterns on the first recessed top surface and the second recessed top surface, respectively, wherein an edge portion of the first recessed top surface has a first height, and an edge portion of the second recessed top surface has a second height, and wherein the metal etching process is performed such that a difference between the second height and the first height is less than about 10 nm.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication number
US20260262240A1
Application number
19659243
Filed
Apr 27, 2026
Published
Sep 3, 2026
Inventors
3
Claims
20

Classified under

H10D 30/43 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.