Samsung patents memory chip design using air gaps to separate layers
Samsung describes a semiconductor memory device where stacked gate electrodes are separated by an air gap within a trench. This structure includes a channel structure and source plate that connect to the gates, with the air gap spanning both the main cell array and an extension region. The design aims to improve the physical layout of the memory cells.
In the filing’s own words
A semiconductor memory device includes a cell lower insulating layer including a cell array region and an extension region, a plurality of gate electrodes stacked on the cell lower insulating layer, a channel structure penetrating the plurality of gate electrodes, a word line contact on the extension region and penetrating a portion of gate electrodes, defining a gate isolation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction, an air gap between the plurality of gate electrodes and in the gate isolation trench, a source plate structure defining an opening communicatively coupled to the gate isolation trench, on one end of the channel structure, and extending in a second horizontal direction, and a cell upper insulating layer on the source plate structure and covering the opening. The air gap is on the cell array region and the extension region.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a cell lower insulating layer comprising a cell array region and an extension region; a plurality of gate electrodes stacked spaced apart from each other on the cell lower insulating layer; a channel structure on the cell array region and penetrating the plurality of gate electrodes; a word line contact on the extension region and penetrating a portion of gate electrodes among the plurality of gate electrodes; the semiconductor memory device defining a gate isolation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction; an air gap between the plurality of gate electrodes and in the gate isolation trench; a source plate structure defining an opening communicatively coupled to the gate isolation trench, the source plate structure on one end of the channel structure and extending in a second horizontal direction that intersects the first horizontal direction; and a cell upper insulating layer on the source plate structure and covering the opening, wherein the air gap is on the cell array region and the extension region.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
- Publication number
- US20260262223A1
- Application number
- 19311546
- Filed
- Aug 27, 2025
- Published
- Sep 3, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 43/35 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 80/312 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.