Samsung patents stacked memory chip with improved top contact design
Samsung describes a method for building vertical memory chips by stacking layers of insulating and conductive materials. The design creates a stepped structure at the top of the stack to help a vertical electrical contact connect securely to the highest layer. This approach aims to improve the reliability of the connection in densely packed memory devices.
In the filing’s own words
A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, comprising: alternately and repeatedly forming first insulation layers and first sacrificial layers on a substrate; forming a second sacrificial layer pattern on an upper portion of an uppermost first sacrificial layer; forming a first hole passing through the second sacrificial layer pattern, the first sacrificial layers, and the first insulation layers; etching portions of the first sacrificial layers and the second sacrificial layer pattern exposed by a sidewall of the first hole to form a first recess positioned at an uppermost portion and communicated with the sidewall of the first hole, and second recesses positioned below the first recess and having a vertical height less than a vertical height of the first recess; forming a third sacrificial layer pattern filling only each of the second recesses and having an etching selectivity respect to each of the first sacrificial layer, the second sacrificial layer pattern, and the first insulation layer; forming a fourth sacrificial layer pattern filling a portion of the first recess; replacing the third sacrificial layer pattern with a second insulation pattern; replacing the first sacrificial layer, the second sacrificial layer pattern, and the fourth sacrificial layer pattern with gate patterns; and forming a through cell contact filling the first hole and contacting only an uppermost gate pattern among the gate patterns.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- VERTICAL MEMORY DEVICE
- Publication number
- US20260262222A1
- Application number
- 19653788
- Filed
- Apr 21, 2026
- Published
- Sep 3, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 43/27 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/40 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 41/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.