Samsung patents 3D memory layout with stepped bit lines
Samsung describes a semiconductor design where bit lines have different heights to accommodate back gates and word lines in a stacked structure. The filing details how these components connect to active patterns and storage cells to organize data in a vertical chip.
In the filing’s own words
A semiconductor device includes a bit line structure extending in a first direction, first, second, and third active patterns sequentially arranged on and connected to the bit line structure, a back gate structure between the first and second active patterns including a back gate dielectric layer and a back gate electrode, and a word line structure between the second and third active patterns. Contact patterns are disposed on and connected to the active patterns, and an information storage structure is disposed on the contact patterns. The bit line structure includes a first portion vertically overlapping the back gate structure and a second portion vertically overlapping the word line structure, with upper surfaces of the first and second portions disposed at different levels.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a bit line structure extending in a first direction; back gate structures disposed on the bit line structure and respectively including a back gate electrode; word line structures disposed alternately with the back gate structures in the first direction, each of the word line structures including a first word line and a second word line, adjacent to each other in the first direction; active patterns disposed between the back gate structures and the word line structures and connected to the bit line structure; contact patterns disposed on each of the active patterns and connected to each of the active patterns; and information storage structures disposed on the contact patterns, wherein the bit line structure includes a first portion vertically overlapping each of the back gate structures, a second portion vertically overlapping each of the word line structures, and a third portion contacting each of the active patterns between the first portion and the second portion and having an inclined surface.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260262216A1
- Application number
- 19535405
- Filed
- Feb 10, 2026
- Published
- Sep 3, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/05 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 90/26 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.