Samsung patents 3D chip layout with stacked layers and vertical wiring
Samsung describes a 3D semiconductor design where two sets of circuit patterns sit side-by-side on a base, separated by insulating layers. Vertical wires, called bit lines, run through the structure to connect these layers, allowing data to move up and down the chip.
In the filing’s own words
A three-dimensional semiconductor device includes: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction; second semiconductor patterns adjacent to the first semiconductor patterns in a second direction, and spaced apart from each other in the first direction; a lower liner pattern disposed on the substrate and extending in the first direction between the first semiconductor patterns and the second semiconductor patterns; an upper liner pattern extending in the first direction on the lower liner pattern; and bit lines disposed between the first semiconductor patterns and the upper liner pattern, and between the second semiconductor patterns and the upper liner pattern, where the bit lines extend in a third direction on the lower liner pattern.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor device comprising: a substrate; a plurality of first semiconductor patterns on the substrate and spaced apart from each other in a first direction parallel to a lower surface of the substrate; a plurality of second semiconductor patterns (i) adjacent to the plurality of first semiconductor patterns in a second direction perpendicular to the first direction and parallel to the lower surface of the substrate, and (ii) spaced apart from each other in the first direction; a lower liner pattern on the substrate and extending in the first direction between the plurality of first semiconductor patterns and the plurality of second semiconductor patterns; an upper liner pattern extending in the first direction on the lower liner pattern; and a plurality of bit lines between (i) the plurality of first semiconductor patterns and the (ii) upper liner pattern, and between (i) the plurality of second semiconductor patterns and (ii) the upper liner pattern, wherein the plurality of bit lines extend, on the lower liner pattern, in a third direction perpendicular to the first direction and the second direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number
- US20260262213A1
- Application number
- 19431001
- Filed
- Dec 23, 2025
- Published
- Sep 3, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10B 12/30 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.