Samsung patents chip packaging design with tapered metal layers
Samsung describes a semiconductor package where a chip sits on a base with metal wiring, covered by a protective layer. The design features a specific shape for the bottom metal layer, which tapers upward and connects to vertical wires to improve electrical contact.
In the filing’s own words
A semiconductor package includes a redistribution structure that includes a lower insulating layer, redistribution layers in the lower insulating layer, and first vias connected to the redistribution layers. The semiconductor package further includes a semiconductor chip on an upper surface of the redistribution structure and electrically connected to the redistribution layers; an interconnection structure on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers, and second vias connecting the interconnection layers to each other; an encapsulant covering the semiconductor chip and the interconnection structure; and external connection conductors on a lower surface of the redistribution structure and electrically connected to the redistribution layers. A lowermost interconnection layer includes a first conductive layer contacting a second via and tapered toward the upper surface, and a second conductive layer surrounding the first conductive layer and in contact with a first via.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a redistribution structure having an upper surface and a lower surface opposing each other, wherein the redistribution structure includes a lower insulating layer, a plurality of redistribution layers disposed in the lower insulating layer, and a plurality of first vias connected to the plurality of redistribution layers, respectively; a semiconductor chip disposed on the upper surface of the redistribution structure and electrically connected to the plurality of redistribution layers; an interconnection structure disposed on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers disposed in the upper insulating layer, and a plurality of second vias connecting the plurality of interconnection layers to each other; an encapsulant covering at least a portion of each of the semiconductor chip and the interconnection structure on the upper surface of the redistribution structure; and a plurality of external connection conductors disposed on the lower surface of the redistribution structure and electrically connected to the plurality of redistribution layers, wherein a lowermost interconnection layer adjacent to the upper surface of the redistribution structure among the plurality of interconnection layers includes: a first conductive layer that contacts one second via of the plurality of second vias and is tapered toward the upper surface, and a second conductive layer that surrounds the first conductive layer and contacts one first via of the plurality of first vias.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package and method of manufacturing a semiconductor package
- Patent number
- US12772915B2
- Application number
- 18662240
- Filed
- May 13, 2024
- Granted
- Oct 20, 2026
- Inventors
- 2
- Claims
- 16
Classified under
H10W 90/401 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/66 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 70/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.