Samsung patents chip making method to keep wafer edges even
This patent describes a way to make computer chips by trimming the edges of a silicon wafer before attaching it to a support base. The process adds a protective layer to the edges and carefully removes material to reveal vertical electrical connections, ensuring the final chips have consistent thickness.
In the filing’s own words
A method for manufacturing semiconductor device includes preparing a semiconductor wafer including a first semiconductor substrate and a first through silicon via; removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region; attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate; forming an edge protection layer along the remaining edge region; exposing the first through silicon via by removing a predetermined depth of the first semiconductor substrate; forming a second final passivation layer to expose the upper surface of the first through silicon via; forming a plurality of first upper connection pads on the second final passivation layer; and dicing the semiconductor wafer into a plurality of first semiconductor chips.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, the method comprising: preparing a semiconductor wafer including a first semiconductor substrate and a first through silicon via, wherein the first through silicon via includes a lower end disposed in the first semiconductor substrate and an upper surface opposite to the lower end; removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region; attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate; forming an edge protection layer along the remaining edge region; exposing the first through silicon via by removing a predetermined depth of the first semiconductor substrate; forming a second final passivation layer to expose the upper surface of the first through silicon via; forming a plurality of first upper connection pads on the second final passivation layer, where the plurality of first upper connection pads are electrically connected to the first through silicon via; and dicing the semiconductor wafer into a plurality of first semiconductor chips.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Method for manufacturing semiconductor devices without thickness deviation
- Patent number
- US12772904B2
- Application number
- 18320013
- Filed
- May 18, 2023
- Granted
- Oct 20, 2026
- Inventors
- 6
- Claims
- 18
Classified under
H10W 90/00 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 74/114 Electricity & electronicsH10W 74/00 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.