Samsung patents chip layer design with hydrogen-supplying oxide coating
Samsung describes a semiconductor structure where metal wiring layers are stacked with insulating materials between them. The top layer includes a specific oxide coating that releases hydrogen and has a thickness ratio designed to smooth out surface steps.
In the filing’s own words
A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: lower metal wirings on a substrate, the lower metal wirings stacked in a plurality of layers; a first upper insulating interlayer on the lower metal wirings; a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer; a second upper insulating interlayer on the first upper insulating interlayer, the second upper insulating interlayer covering the first upper metal pattern; an uppermost wiring including an uppermost via in the second upper insulating interlayer and an uppermost metal pattern on the second upper insulating interlayer; and an oxide layer for supplying hydrogen on the second upper insulating interlayer, the oxide layer for supplying hydrogen covering the uppermost wiring, wherein a thickness of the uppermost via is less than 40% of a thickness of the uppermost metal pattern, and wherein a thickness of a portion of the oxide layer located on a top surface of the uppermost metal pattern is greater than 40% of the thickness of the uppermost metal pattern and is less than the thickness of the uppermost metal pattern, and wherein an upper surface of the oxide layer includes a step difference that is lower than a step difference between the top surface of the uppermost metal pattern and a top surface of the second upper insulating interlayer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12772832B2
- Application number
- 18209820
- Filed
- Jun 14, 2023
- Granted
- Oct 20, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 20/425 Electricity & electronicsH10W 20/43 Electricity & electronicsH10W 20/47 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.