Samsung patents chip layout that links different transistor zones
Samsung describes a semiconductor design where specific areas of a chip are electrically linked to improve performance. The filing details how different sections of the chip, known as active regions, are connected through metal pathways to manage electrical flow.
In the filing’s own words
A semiconductor device includes a substrate doped with first conductivity-type impurities, a first well doped with second conductivity-type impurities different from the first conductivity-type impurities, first active regions in the first well, the first active regions being doped with the first conductivity-type impurities and connected to a first pad through a first interconnection, second active regions outside the first well, the second active regions being doped with the second conductivity-type impurities and connected to a second pad through a second interconnection, third active regions around the first active regions in the first well and doped with the second conductivity-type impurities, and fourth active regions around the second active regions outside the first well and doped with the first conductivity-type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate doped with first conductivity-type impurities; a first well region in the substrate and doped with second conductivity-type impurities, the second conductivity-type impurities being different from the first conductivity-type impurities; first active regions in the first well region, the first active regions being doped with the first conductivity-type impurities, and being connected to a first pad through a first interconnection pattern; second active regions outside of the first well region in the substrate, the second active regions being doped with the second conductivity-type impurities, and being respectively connected to a second pad through a second interconnection pattern; third active regions around the first active regions in the first well region and doped with the second conductivity-type impurities; and fourth active regions around the second active regions outside the first well region and doped with the first conductivity-type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12772571B2
- Application number
- 18582871
- Filed
- Feb 21, 2024
- Granted
- Oct 20, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 89/713 Electricity & electronicsH10D 62/106 Electricity & electronicsH10D 84/135 Electricity & electronicsH10D 84/617 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.