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Samsung patents chip layout method to improve alignment accuracy

Patent drawing
Patent drawing from the official filing.

This patent describes a method for designing the physical layout of integrated circuits. It uses specific alignment patterns in non-functional areas of the chip to ensure that different layers of the circuit, such as gates and contacts, are placed precisely on top of each other during manufacturing.

Why it mattersThis is a routine improvement in semiconductor manufacturing that helps ensure chips are built correctly, but it does not describe a new consumer feature or product.

In the filing’s own words

A layout design method includes: designing a gate layout including a gate pattern in a first region and a gate alignment key pattern in a second region; designing a contact layout including a contact pattern in a first region and a contact alignment key pattern in a second region; and designing a contact cut layout including a contact cut pattern for cutting a portion of the contact pattern and for cutting a portion of the contact alignment key pattern, wherein the contact alignment key pattern includes a gate-contact overlay pattern that overlaps the gate alignment key pattern, and the contact cut pattern includes a gate-contact overlay cut pattern that overlaps the gate-contact overlay pattern.

What exactly they claim (claim 1)

1. A layout design method comprising: designing a gate layout comprising a gate pattern in a first region and a gate alignment key pattern in a second region; designing a contact layout comprising a contact pattern in a first region and a contact alignment key pattern in a second region; and designing a contact cut layout comprising a contact cut pattern for cutting a portion of the contact pattern and for cutting a portion of the contact alignment key pattern, wherein the contact alignment key pattern comprises a gate-contact overlay pattern that overlaps the gate alignment key pattern, and the contact cut pattern comprises a gate-contact overlay cut pattern that overlaps the gate-contact overlay pattern.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Layout design method and integrated circuit device manufacturing method using the same
Patent number
US12772569B2
Application number
18389905
Filed
Dec 20, 2023
Granted
Oct 20, 2026
Inventors
1
Claims
20

Classified under

H10D 89/10 Electricity & electronicsG06F 30/392 Physics & computingG06F 30/398 Physics & computingH10P 76/00 Electricity & electronicsH10W 46/00 Electricity & electronicsG06F 2119/18 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.