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Samsung patents chip design that bonds two silicon wafers with trenches

Samsung describes an integrated circuit where a second silicon wafer is attached to the back of a first wafer using a pattern of small trenches and bonding areas. This structure allows electrical connections to be made through the back of the chip rather than just the front.

Why it mattersThis technique could help engineers pack more components into smaller chips by utilizing space on the backside of the silicon.

In the filing’s own words

An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.

What exactly they claim (claim 1)

1. An integrated circuit device comprising: a first semiconductor substrate having a frontside surface and a backside surface that are opposite to each other; a front-end-of-line (FEOL) structure on the frontside surface of the first semiconductor substrate, the FEOL structure comprising a plurality of fin-type active areas; a first back-end-of-line (BEOL) structure on the FEOL structure, the first BEOL structure apart from the first semiconductor substrate in a vertical direction with the FEOL structure therebetween; a second BEOL structure on the backside surface of the first semiconductor substrate, the second BEOL structure apart from the FEOL structure in the vertical direction with the first semiconductor substrate therebetween; and a second semiconductor substrate apart from the first semiconductor substrate in the vertical direction with the FEOL structure and the first BEOL structure therebetween, the second semiconductor substrate locally bonded to the first BEOL structure, wherein the second semiconductor substrate comprises a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a plurality of local trench regions in which a plurality of trenches are arranged in a regular pattern and a plurality of local bonding areas bonded to the first BEOL structure.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Integrated circuit device
Patent number
US12772560B2
Application number
18760724
Filed
Jul 1, 2024
Granted
Oct 20, 2026
Inventors
6
Claims
20

Classified under

H10D 84/907 Electricity & electronicsH10D 84/953 Electricity & electronicsH10D 84/981 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.