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Samsung patents 3D chip design with variable-length channels for better stacking

Patent drawing
Patent drawing from the official filing.

Samsung has been granted a patent for a 3D-stacked semiconductor device that uses different channel lengths in its upper and lower layers. The design includes specific spacer components that adjust in size to accommodate the shorter channel in the top layer, allowing for more compact vertical stacking of transistors.

Why it mattersThis technique helps manufacturers pack more transistors into smaller spaces, which is a standard approach for improving the density and performance of future computer chips.

In the filing’s own words

Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1 st source/drain region connected to a 1 st channel structure; and a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure, wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in a channel-length direction, in which the 2 nd source/drain region is connected to a 3 rd source/drain region through the 2 nd channel structure.

What exactly they claim (claim 1)

1. A three-dimension (3D) stacked semiconductor device comprising: a 1 st source/drain region connected to a 1 st channel structure; a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure; a gate structure surrounding the 1 st channel structure and the 2 nd channel structure; a 1 st inner spacer between a 1 st portion of the gate structure and the 1 st source/drain region; and a 2 nd inner spacer between a 2 nd portion of the gate structure and the 2 nd source/drain region, wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in a channel-length direction, in which the 2 nd source/drain region is connected to a 3 rd source/drain region through the 2 nd channel structure, wherein the 2 nd inner spacer has a smaller length than the 1 st inner spacer in the channel-length direction, and wherein the 2 nd source/drain region has a greater length than the 1 st source/drain region in the channel-length direction.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
3D-stacked semiconductor device manufactured using channel spacer
Patent number
US12772556B2
Application number
18380476
Filed
Oct 16, 2023
Granted
Oct 20, 2026
Inventors
3
Claims
16

Classified under

H10D 84/856 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.