Samsung patents chip layout with extra insulation between memory lines
This patent describes a specific arrangement for memory chips where wires called bitlines are separated by small walls of insulating material. It also places vertical insulating layers between these walls and the electrical connections to the memory cells.
In the filing’s own words
An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a substrate comprising a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between, and spaced apart from, adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Integrated circuit device
- Patent number
- US12772535B2
- Application number
- 18371869
- Filed
- Sep 22, 2023
- Granted
- Oct 20, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 64/513 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.