Samsung patents 3D memory structure with bent internal wiring

1. A semiconductor memory device, comprising: a substrate; gate electrodes stacked on the substrate, the gate electrodes being spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; channel structures penetrating through the gate electrodes, the channel structures extending in the first direction and including channel layers, respectively; a horizontal conductive layer below the gate electrodes on the substrate, the horizontal conductive layer being in contact with the channel layers of the channel structures; separation regions penetrating through the gate electrodes and the horizontal conductive layer, the separation regions extending in the first direction and in a second direction perpendicular to the first direction, and the separation regions being spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a cell region insulating layer covering the gate electrodes and the channel structures; an upper support layer on the separation regions and on the cell region insulating layer, the upper support layer having openings that overlap portions of the separation regions; and conductive pad layers in the openings, respectively, wherein each of the separation regions includes a contact conductive layer and a first separation insulating layer in a trench, and each of the separation regions has first regions below the openings and second regions alternating with the first regions, wherein the contact conductive layer is in contact with the substrate in the first regions, and is spaced apart from the substrate by the first separation insulating layer in the second regions, wherein each of the separation regions has a bent portion having a width in the third direction, wherein the width of the bent portion changes along the first direction below a corresponding one of the openings, wherein the bent portion is positioned at a higher vertical level than a vertical level of an uppermost gate electrode of the gate electrodes stacked on the substrate, wherein the conductive pad layers are connected to the contact conductive layer, and wherein for each of the separation regions, the bent portion and the uppermost gate electrode are separated by a gap.