Samsung patents chip design with vertical connections to reduce wiring space
This patent describes a method for building computer chips where electrical connections run vertically through the silicon layers. It uses a specific shape for the semiconductor material to help connect the top of the chip to the wiring underneath.
In the filing’s own words
An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a rear wiring structure; an insulating substrate disposed on the rear wiring structure and including a plurality of fin structures extending in a first horizontal direction; a device isolation layer disposed between the plurality of fin structures; a lower insulating layer covering top surfaces of the plurality of fin structures; a plurality of gate structures extending in a second horizontal direction crossing the first horizontal direction on the insulating substrate; a plurality of nanosheet stacks disposed on the lower insulating layer and at least partially surrounded by the plurality of gate structures; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and at least partially passes through a corresponding one of the plurality of fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure; wherein a sidewall of the semiconductor epitaxial structure comprises a portion with a positive profile that extends to increase a width of the semiconductor epitaxial structure in the first horizontal direction as the sidewall of the semiconductor epitaxial structure moves away from a bottom surface of the lower insulating layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Integrated circuit device including a field-effect transistor having a semiconductor epitaxial structure and method of manufacturing the same
- Patent number
- US12772528B2
- Application number
- 18513759
- Filed
- Nov 20, 2023
- Granted
- Oct 20, 2026
- Inventors
- 6
- Claims
- 17
Classified under
H10D 64/017 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.