Samsung patents chip design that blocks unwanted electrical connections
This patent describes a specific layout for a semiconductor transistor that uses a physical barrier to control where electrical contacts can be made. By placing a blocking pattern under one of the source/drain regions, the design ensures that the electrical connection stops at a precise depth, preventing it from extending too far down into the chip.
In the filing’s own words
A semiconductor device includes a substrate, a first sheet pattern on the substrate, a gate electrode on the substrate and surrounding the first sheet pattern, a first source/drain pattern and a second source/drain pattern respectively connected to a first end and a second end of the first sheet pattern, a contact blocking pattern on a lower side of the second source/drain pattern, a first source/drain contact extending in a first direction and connected to the first source/drain pattern, and a second source/drain contact connected to the second source/drain pattern and extending in the first direction to contact an upper surface of the contact blocking pattern. A depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact may be greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including an upper surface and a lower surface that are opposite each other in a first direction; a first sheet pattern on the upper surface of the substrate, the first sheet pattern including a first end and a second end; a gate electrode extending in a second direction on the upper surface of the substrate, the gate electrode surrounding the first sheet pattern; a first source/drain pattern connected to the first end of the first sheet pattern; a second source/drain pattern connected to the second end of the first sheet pattern; a contact blocking pattern on a lower side of the second source/drain pattern, the contact blocking pattern including an upper surface and a lower surface that are opposite each other in the first direction; a first source/drain contact extending in the first direction, the first source/drain contact being connected to the first source/drain pattern; and a second source/drain contact in contact with the upper surface of the contact blocking pattern, the second source/drain contact extending in the first direction, and the second source/drain contact being connected to the second source/drain pattern, wherein a depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact is greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device
- Patent number
- US12772498B2
- Application number
- 18334849
- Filed
- Jun 14, 2023
- Granted
- Oct 20, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 30/6729 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsH10W 20/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.