Samsung patents chip method that adds insulation at the base of stacked layers
Samsung describes a way to build computer chips by stacking thin sheets of semiconductor material on top of a base structure. The process uses temporary layers that are removed to create space, which is then filled with insulating material at the very bottom of the stack to separate the components.
In the filing’s own words
A method of manufacturing an integrated circuit device includes forming, on a substrate, a fin-type active region and a stack structure in which sacrificial semiconductor layers and nanosheet semiconductor layers are alternately stacked one-by-one, forming a first local liner on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer, which is closest to the fin-type active region and expose sidewalls of other sacrificial semiconductor layers, forming a second local liner on the sidewall of the stack structure to cover the sidewalls of the other sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer, exposing the bottom sacrificial semiconductor layer by removing the first local liner, forming a bottom insulating space exposing a fin top surface of the fin-type active region by removing the bottom sacrificial semiconductor layer, and forming a bottom insulating structure in the bottom insulating space.
What exactly they claim (claim 1)
1. A method of manufacturing an integrated circuit device, the method comprising: forming a fin-type active region on a substrate; forming, on the fin-type active region, a stack structure in which a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers are alternately stacked one-by-one; forming a first local liner on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer, the bottom sacrificial semiconductor layer being a sacrificial semiconductor layer closest to the fin-type active region from among the plurality of sacrificial semiconductor layers, and expose sidewalls of other sacrificial semiconductor layers, the other sacrificial semiconductor layers being sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer from among the plurality of sacrificial semiconductor layers; forming a second local liner on the sidewall of the stack structure to cover sidewalls of the other sacrificial semiconductor layers; exposing the bottom sacrificial semiconductor layer by removing the first local liner; forming a bottom insulating space to expose a fin top surface of the fin-type active region by removing the bottom sacrificial semiconductor layer; and forming a bottom insulating structure to fill the bottom insulating space such that an outer sidewall of the bottom insulating structure is coplanar with a sidewall of the stack structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Method of manufacturing integrated circuit device
- Patent number
- US12772476B2
- Application number
- 18497446
- Filed
- Oct 30, 2023
- Granted
- Oct 20, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 64/01 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.