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Samsung patents chip packaging method using light-sensitive glue

Patent drawing
Patent drawing from the official filing.

Samsung has been granted a patent for a specific way to build semiconductor packages. The design uses a light-sensitive epoxy resin to fill the gap between the chip and the base, along with a protective layer on the side of the chip's connection points.

Why it mattersThis filing details a specific manufacturing technique for securing chips, which is a routine improvement in how electronics are assembled rather than a new consumer feature.

In the filing’s own words

A semiconductor package and a method of fabricating the same. The semiconductor package includes a lower structure including a first lower conductive pad disposed on an upper surface thereof, a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof, a solder ball connecting the first lower conductive pad and the first chip conductive pad, a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip, and a first organic insulating layer covering a side surface of the first chip conductive pad.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a lower structure including a first lower conductive pad disposed on an upper surface thereof; a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof; a solder ball connecting the first lower conductive pad and the first chip conductive pad; a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip; and a first organic insulating layer covering a side surface of the first chip conductive pad, wherein the photosensitive insulating layer includes an epoxy resin, a dissolution inhibitor, a curing agent, and a filler.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor package and method of fabricating the same
Patent number
US12772461B2
Application number
18205721
Filed
Jun 5, 2023
Granted
Oct 20, 2026
Inventors
2
Claims
18

Classified under

H10B 80/00 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 72/01204 Electricity & electronicsH10W 72/01215 Electricity & electronicsH10W 72/01304 Electricity & electronicsH10W 72/01351 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.