Samsung patents 3D memory layout that stacks capacitors over transistors
This patent describes a specific way to arrange the tiny switches and storage dots inside a memory chip. It places a capacitor directly above a contact point that connects to a transistor, allowing the components to be stacked vertically to save space.
In the filing’s own words
A semiconductor device may include first and second active patterns, first and second gate structures, a source/drain layer, a bit line structure, a contact plug structure, and a capacitor. The first and second active patterns are on a cell region and a peripheral circuit region of a substrate, respectively. The first gate structure extends through an upper portion of the first active pattern. The second gate structure is on an upper surface and an upper sidewall of the second active pattern. The source/drain layer is on a portion of the second active pattern that is adjacent to the second gate structure. The bit line structure is on a central portion of the first active pattern, and overlaps the second gate structure in a horizontal direction. The contact plug structure is on opposing end portions of the first active pattern. The capacitor is on the contact plug structure.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: first and second active patterns on a cell region and a peripheral circuit region of a substrate, respectively; a first gate structure that extends through an upper portion of the first active pattern; a second gate structure on an upper surface and an upper sidewall of the second active pattern; a source/drain layer on a portion of the second active pattern that is adjacent to the second gate structure; a bit line structure on a central portion of the first active pattern, the bit line structure overlapping the second gate structure in a horizontal direction that is substantially parallel to an upper surface of the substrate; a contact plug structure on opposing end portions of the first active pattern; and a capacitor on the contact plug structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device
- Patent number
- US12772435B2
- Application number
- 18616352
- Filed
- Mar 26, 2024
- Granted
- Oct 20, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.