Samsung patents chip method that uses timers to sync data between cores
This patent describes a way for multiple processing cores in a chip to share data without constantly checking on each other. Instead of waiting for a specific signal, the system uses a timer to automatically update the status of shared data after a set period.
In the filing’s own words
A method includes forwarding, by a first core, a read request for a cache line to a first cache, forwarding, by the first cache, a Set-timeout shared-state request to a directory in response to the read request, forwarding, by the directory, the Set-timeout shared-state request to a second cache, in response to the Set-timeout shared-state request, changing a state of the cache line of the second core to a Shared state and forwarding a Shared-accepted response to the first cache and the directory, by the second cache, changing a state of the cache line of the directory and a state of the cache line of the first core to the Shared state, and performing a timeout to change a state of the cache line of the directory and a state of the cache line of the first core, in response to reaching a predetermined time.
What exactly they claim (claim 1)
1. An operating method of a multi-core processor comprised of a first core and a second core, the operating method comprising: forwarding, by the first core, a read request for a cache line to a first cache corresponding to the first core; forwarding, by the first cache, a Set-timeout shared-state request to a directory, in response to the read request; forwarding, by the directory, the Set-timeout shared-state request to a second cache corresponding to the second core; in response to the Set-timeout shared-state request, changing a state of the cache line of the second core to a Shared state and forwarding, by the second cache, a Shared-accepted response to the first cache and the directory; changing a state of the cache line of the directory and a state of the cache line of the first core to the Shared state; and performing a timeout, and in response to the timeout reaching a predetermined time, changing a state of the cache line of the directory and a state of the cache line of the first core.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Multi-core processor with timeout-based cache coherence
- Patent number
- US12769662B2
- Application number
- 19176030
- Filed
- Apr 10, 2025
- Granted
- Oct 20, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G06F 12/0828 Physics & computingG06F 2212/621 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.