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SamsungGranted patentChips & hardwareInterest 6/10

Samsung patents stacked chip design with embedded connection points

Patent drawing
Patent drawing from the official filing.

Samsung describes a method for building 3D integrated circuits by stacking one chip die on top of another. The design uses a base layer with specific connection points that fit entirely within the footprint of the top chip, allowing for a compact, layered structure.

Why it mattersThis layout technique helps manufacturers create smaller, more efficient processors by stacking components vertically rather than spreading them out.

In the filing’s own words

A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.

What exactly they claim (claim 1)

1. A three-dimensional (3D) integrated circuit structure, comprising: a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material surrounding the first semiconductor chip die and the plurality of core balls; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure, wherein a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die, wherein the first semiconductor chip die comprises upper bonding pads.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
3D integrated circuit (3DIC) structure and method for manufacturing the same
Patent number
US12765435B2
Application number
18493166
Filed
Oct 24, 2023
Granted
Oct 13, 2026
Inventors
3
Claims
20

Classified under

H10W 90/701 Electricity & electronicsH10W 70/05 Electricity & electronicsH10W 70/093 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/01 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.