Samsung patents chip package with edge-based wiring connections
This patent describes a semiconductor package design where electrical connections are routed through the outer edges of the chip substrate rather than just the center. It uses vertical holes called through vias in the edge area to link wiring on the top and bottom surfaces of the chip. This layout keeps the main processing area clear for other components.
In the filing’s own words
A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a first semiconductor substrate that has a device region and an edge region; a first semiconductor element on the device region, wherein the first semiconductor element is formed on an active surface of the first semiconductor substrate; a first circuit layer disposed on the active surface of the first semiconductor substrate; a first redistribution layer disposed on the first circuit layer; and a plurality of first through vias on the edge region, wherein the plurality of first through vias vertically penetrate the first semiconductor substrate and the first circuit layer and are connected to the first redistribution layer, wherein the first circuit layer includes: a first device interlayer dielectric layer that covers the active surface of the first semiconductor substrate; and a first circuit wiring pattern on the device region, wherein the first circuit wiring pattern is provided in the first device interlayer dielectric layer and connected to the first semiconductor element, wherein the first circuit wiring pattern and the plurality of first through vias are electrically connected through the first redistribution layer, and wherein the plurality of first through vias are arranged in at least two columns that extend along an outer edge of the first semiconductor substrate and that are spaced apart from each other in a direction from the device region toward the outer edge of the first semiconductor substrate.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package
- Patent number
- US12765407B2
- Application number
- 18368646
- Filed
- Sep 15, 2023
- Granted
- Oct 13, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 70/685 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 70/60 Electricity & electronicsH10W 70/656 Electricity & electronicsH10W 90/722 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.