Samsung patents chip package design with vertical connections
Samsung has been granted a patent for a specific way to build semiconductor packages. The design places a chip on a base layer with wiring, covers it with a sealing material, and uses vertical metal structures to connect the base wiring to a top layer of wiring.
In the filing’s own words
A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a lower redistribution wiring layer having a first region and a second region adjacent the first region, the lower redistribution wiring layer including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern in a marking layer of the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are in the marking layer and exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer including a layer of second redistribution wirings electrically connected to the plurality of vertical conductive structures, wherein the layer of second redistribution wiring is on the sealing member and the marking layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package and method of manufacturing the semiconductor package
- Patent number
- US12765392B2
- Application number
- 18515797
- Filed
- Nov 21, 2023
- Granted
- Oct 13, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10W 46/00 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/701 Electricity & electronicsH10W 46/401 Electricity & electronicsH10W 70/60 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.