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Samsung patents chip wiring layers with different grain sizes

This patent describes a method for building the metal connections inside a computer chip. It uses two layers of material in the wiring channels, where the top layer has larger crystal grains than the bottom layer to improve the structure.

Why it mattersThis is a detailed engineering improvement to how electrical connections are made inside microchips, which helps manufacturers build more reliable processors.

In the filing’s own words

An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

What exactly they claim (claim 1)

1. An integrated circuit device comprising: a source/drain contact insulation layer on a lower structure; a source/drain contact via penetrating through the source/drain contact insulation layer; an interconnect wiring insulation layer on the source/drain contact insulation layer, the interconnect wiring insulation layer including an interconnect wiring trench exposing a top surface of the source/drain contact via; a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench, the first interconnect wiring layer including a first precursor; and a second interconnect wiring layer on the first interconnect wiring layer, the second interconnect wiring layer covering an upper portion of the sidewall of the interconnect wiring trench, and the second interconnect wiring layer including a second precursor, wherein a crystal grain size of the second precursor is larger than a crystal grain size of the first precursor.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Integrated circuit device
Patent number
US12765365B2
Application number
18650288
Filed
Apr 30, 2024
Granted
Oct 13, 2026
Inventors
6
Claims
20

Classified under

H10W 20/435 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6211 Electricity & electronicsH10D 30/6219 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.